1. Technical Field of the Invention
The present invention relates to a buffer for storing information, such as packetized data.
2. Description of the Related Art
Driven by growing bandwidth demands from the ever-increasing population of network users, there is a relatively large market for various kinds of networking 10 equipment. Among them, packet networking systems such as packet switches and routers are the key building blocks of networking infrastructures.
Generally, a packet switch/router performs two major functions: packet routing and forwarding. The former looks up the route-table to decide where an incoming packet will be forwarded (i.e., by which output port of the switch/router that the packet will leave); and the latter executes the actual forwarding operations. Before a packet can be forwarded to the next hop, due to resource contentions or other reasons, it may need to be stored in a packet buffer somewhere in the switch/router. In order to absorb temporary traffic congestions, fast and dense packet buffers are indispensable for the building of a high-performance fast packet switches/routers. Further, intensive research on high-speed switches/routers in the past decade have revealed that packet buffers used in a switch/router constitute a bottleneck for cost reducing and performance improving. Up to now, it still remains a difficult challenge to make fast and dense packet buffers which meet the needs of high-speed networking applications.
Packet buffers are generally solid-state random access memories (RAM) built by CMOS technologies. Generally speaking, those CMOS RAMs can be classified into two major categories: static random access memory (SRAM) and dynamic random access memory (DRAM). The former is faster and the latter is denser. On one hand, one can build a fast and small buffer using SRAM; on the other hand, one can build a slow and dense buffer using DRAM. However, neither pure SRAM nor pure DRAM can build a desired fast and dense packet buffer.
A two-hierarchy SRAM+DRAM architecture was previously proposed in the art to build a first-in-first out (FIFO) fast and dense packet buffer. In this architecture, a DRAM provides the main storage capacity and a small SRAM is located between the external access interface and the DRAM to serve as a cache for access acceleration. Further, special properties held by FIFO packets are utilized to pipeline the operations of SRAM and DRAM. While this solution may represent a right direction for attacking the intended problem, nevertheless, it requires a sophisticated scheduler and limits its applicability to FIFO buffers only, which offsets the benefits obtained from this solution.
Based upon the foregoing, there is a need for a packet buffer which is sufficiently sized to hold a relatively large number of packets, sufficiently fast to accommodate relatively high speed communication and relatively simple in implementation.